DPDK Summit 2025: Full Schedule

8-9 May 2025 | Prague, Czech Republic
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Please note: This schedule is automatically displayed in Central European Time. To see the schedule in your preferred timezone, please select from the drop-down at the bottom of the menu to the right.

The schedule is subject to change.

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08:00 CEST

Registration + Badge Pick-up

Thursday May 8, 2025 08:00 - 17:30 CEST

ABC Ballroom Foyer

Thursday May 8, 2025 08:00 - 17:30 CEST
ABC Ballroom Foyer

Registration/Breaks/Special Events

09:00 CEST

Welcome + Opening Remarks

Thursday May 8, 2025 09:00 - 09:20 CEST

ABC Ballroom

Thursday May 8, 2025 09:00 - 09:20 CEST
ABC Ballroom

Opening/Closing Remarks

09:25 CEST

SORING: A Software Approach for Ordered Parallelism - Francesco Ciaccia & Konstantin Ananyev, Huawei Ireland Research Centre

Thursday May 8, 2025 09:25 - 09:55 CEST

ABC Ballroom

Staged-Ordered-Ring (SORING) is a software abstraction that enables 'ordered' queues with multiple processing stages, built on the familiar DPDK ring concept. It is designed for applications that require a pipeline model for packet processing while preserving the order of incoming packets.

In this presentation, we will explore the internal design of SORING, highlighting its unique features and how it differs from similar approaches. We will also discuss the integration of SORING into an existing Run-To-Completion system, focusing on an ACL (Access Control List) use case. Additionally, we will cover the design challenges, limitations encountered, and the performance results achieved.

Speakers

Francesco Ciaccia

Senior Software Engineer, Huawei Ireland Research Centre

Francesco Ciaccia is a software engineer at the Huawei Ireland Research Centre, working in the Cloud IaaS Network Team and holds a Ph.D in Computer Architecture. With 10 years of experience in software networking, he specializes in high-performance packet processing. Francesco has... Read More →

Konstantin Ananyev

Mr, Huawei Ireland Research Centre

n/a

Thursday May 8, 2025 09:25 - 09:55 CEST
ABC Ballroom

Session Presentations

10:00 CEST

Enhancing Multi-Process DPDK Applications With External Queues for Seamless Offloading - Ori Kam, Nvidia

Thursday May 8, 2025 10:00 - 10:10 CEST

ABC Ballroom

Writing multi-process DPDK applications using external queues" explores a novel approach to leveraging DPDK’s multi-process capabilities without requiring shared data or a designated main process. While DPDK supports offloading flows to hardware for performance gains, integrating offloading logic into existing applications can be challenging. By using APIs that enable one application to register queues with another, users can introduce a separate offloading application without modifying the original one. This approach is particularly valuable in scenarios like P4-based architectures, where the offloading application operates independently from the main application, enabling greater flexibility and modularity

Speakers

Ori Kam

senior staff engineer, Nvidia

I have over 15 years of software development experience and for the last few years, my focus has been contributing to DPDK, where I’m the rte_flow maintainer, and developing DPDK applications. My area of expertise is offloading traffic to the HW.

Thursday May 8, 2025 10:00 - 10:10 CEST
ABC Ballroom

Lightning Talks

10:10 CEST

Break + Networking

Thursday May 8, 2025 10:10 - 10:40 CEST

ABC Ballroom Foyer

Thursday May 8, 2025 10:10 - 10:40 CEST
ABC Ballroom Foyer

Registration/Breaks/Special Events

10:40 CEST

PQC-ML-DSA Processing in DPDK - Dhanalakshmi Saravanan, Marvell Inc & Venkanna Rachakonda, Marvell Technology Inc

Thursday May 8, 2025 10:40 - 11:10 CEST

ABC Ballroom

Quantum computers have the potential to break widely used encryption methods, such as RSA and ECC, through algorithms like Shor's. This poses a serious threat to data security, as sensitive information could be compromised. In response, the security industry is actively developing post-quantum cryptography (PQC). These new algorithms are designed to be resistant to quantum attacks, ensuring that data remains secure even in a quantum computing environment. Traditional cryptography relies on complex problems, such as factoring large integers and discrete logarithms, which can be easily solved by quantum computers using Shor's algorithm. Digital signatures ensure data integrity, authenticate the signer's identity, offer non-repudiation.ML-DSA(FIPS 204) is a suite of algorithms for creating and verifying digital signatures, believed to be secure even against quantum computing threats.
The cryptographic operations of ML-DSA can be accelerated in two ways:
1. Crypto-only acceleration with rte_cryptodev
2. Complete protocol acceleration with rte_security
This session will cover how DPDK enables crypto-only and complete protocol acceleration of ML-DSA using rte_cryptodev and rte_security.

Speakers

Venkanna Rachakonda

Staff Manager SecuritySW, Marvell Technology Inc

My name is Rachakonda Venkanna, and I hold a Master's degree in Computer Science Engineering with over ten years of experience in Cryptography. I have a robust background in implementing and offloading SSL and IPSEC protocols in crypto-accelerated devices, which has enabled me to... Read More →

Dhanalakshmi Saravanan

Director SecuritySW, Marvell Inc, Marvell Inc

Dhanalakshmi Saravanan - Director SecuritySW at Marvell Inc., leads the Crypto and Compliance team. She started her career as hardware design engineer specializing in IPSEC/iSCSI protocol. Her expertise in cryptography has been instrumental in developing end-to-end solutions for payments... Read More →

Thursday May 8, 2025 10:40 - 11:10 CEST
ABC Ballroom

Session Presentations

11:15 CEST

Exploring Network Application Acceleration Using Regex Device Offload - Lukas Sismis, CESNET

Thursday May 8, 2025 11:15 - 11:45 CEST

ABC Ballroom

Regular expression (regex) processing is a critical workload in applications such as network security, log analysis, and deep packet inspection. Traditionally, regex execution is performed in software, often leading to significant CPU overhead and performance bottlenecks. To mitigate this, hardware-based regex acceleration has emerged as a solution, shifting computationally expensive pattern matching tasks to dedicated hardware.
DPDK introduced a regex device API in 2020, providing a standardized application-layer API for management and operation of these devices.

This talk discusses the integration of the DPDK regex API, offering an architectural overview of applications using this interface. We present benchmarks conducted on the regex device in NVIDIA BlueField-2 DPU. Our evaluation includes performance comparisons between the RXP hardware acceleration engine and traditional software libraries, such as Intel's Hyperscan. Additionally, we share our developer experiences, highlighting challenges and best practices encountered during the integration process.
The talk concludes with our view on the use of regex API and its future prospects.

Speakers

Lukas Sismis

Senior researcher, CESNET

Lukas Sismis has been in DPDK community since 2020, focusing on accelerating Suricata, network-baased intrusion detection system.

Thursday May 8, 2025 11:15 - 11:45 CEST
ABC Ballroom

Session Presentations

11:50 CEST

Beyond Standard ASICs: Leveraging Specialized Hardware and DPDK for Next-Gen Networking. - Vitaliy Ivanov, Niagara Networks

Thursday May 8, 2025 11:50 - 12:20 CEST

ABC Ballroom

Niagara Networks provides high-performance, high-reliability network visibility and traffic delivery solutions for the world's most demanding service provider and enterprise environments.

Vitaliy will share Niagara Networks' experience in extending standard ASIC processing capabilities by integrating specialized hardware modules with DPDK applications into a single unit to support advanced functionalities such as:

- Packet and flow slicing
- Traffic deduplication
- NetFlow and IPFIX
- Packet data masking
- Packet RegEx search
- L7 application filtering
- TLS decryption
- GTP 3G/4G traffic correlation

To achieve this, Vitaliy will cover:

- Custom hardware utilizing Ethernet controllers from Intel
- ASIC-to-Ethernet controller backplane connectivity
- OS integration and provisioning for DPDK applications
- Performance and optimization strategies, including:
a. OS tweaks
b. BIOS optimizations
c. DPDK application architecture optimizations
- Testing and CI:
a. Custom framework development
b. CI implementation on test servers instead of final hardware

Speakers

Vitaliy Ivanov

Director of SW Development, Niagara Networks

Director of Software Development at Niagara Networks. With over 20 years of experience in networking and software development, I have worked across diverse domains, including desktop and cross-platform development, low-level and embedded systems, graphical development. However, my... Read More →

Thursday May 8, 2025 11:50 - 12:20 CEST
ABC Ballroom

Session Presentations

12:20 CEST

Lunch Break

Thursday May 8, 2025 12:20 - 13:35 CEST

TBD

Thursday May 8, 2025 12:20 - 13:35 CEST
TBD

Registration/Breaks/Special Events

13:35 CEST

Enhanced Parallel Writing of Nested Data in Columnar Formats in Order of Petabytes - Mohammed Saif, Fishbone Solutions (Project REM)

Thursday May 8, 2025 13:35 - 13:45 CEST

ABC Ballroom

With Increase of high performance data applications require data to written at very high speeds , where traditional Row based systems struggle with the scale and complexity of data. This session explores the usage of DPDK and kernel bypass techniques to massively improve the throughput of I/O operations when scaling in order of PetaBytes. Gives insights and key decisions and trade offs while building and implementing such systems. Using DPDK to enhance parallel writing of nested data in columnar formats at petabyte scale combines the framework’s high-performance ethos with the needs of modern data systems. By leveraging DPDK’s multi-threading, memory management, and hardware acceleration, this approach removes traditional bottlenecks, enabling scalable, efficient data storage for applications from scientific research to big data analytics. As data volumes grow, acceleration techniques are very key to improve efficiency and scaling the system.

Speakers

Mohammed Saif

Mr, Fishbone Solutions (Project REM)

Mohammed Saif is a seasoned data systems engineer at Fishbone Solutions, a division of Project REM Ltd, where he specializes in designing and optimising high-performance data applications for petabyte-scale applications. With a strong foundation in computer science from the University... Read More →

Thursday May 8, 2025 13:35 - 13:45 CEST
ABC Ballroom

Lightning Talks

13:50 CEST

Flow-Get About It: Benchmarking of Flow Timeout Algorithms for Rte_hash Tables - Tobias Roeder, ipoque, a Rohde & Schwarz company

Thursday May 8, 2025 13:50 - 14:00 CEST

ABC Ballroom

In this tech talk, we benchmark connection tracking implementations by extending rte_hash based tables with advanced flow aging mechanisms. We compare aging algorithms like timer wheels, smart periodic scanning vs. LRU tables.
We define test cases based on telco traffic profiles using T-Rex traffic-gen and interpret the benchmark results.
Join us to gain insights into enhancing DPDK rte_hash with flow aging features.

Speakers

Tobias Roeder

Senior Application Engineer, ipoque, a Rohde & Schwarz company

Tobias holds a degree in electrical engineering and has more than ten years of experience in software development. For a number of years, Tobias has been working as an application engineer at ipoque, a subsidiary of the Rohde & Schwarz company. In customer consulting, he identifies... Read More →

Thursday May 8, 2025 13:50 - 14:00 CEST
ABC Ballroom

Lightning Talks

14:05 CEST

Suricata With Rte_flow: Improving the Performance of IPS and IDS With Hardware Acceleration - Adam Kiripolský & Eliška Červinková, Cesnet

Thursday May 8, 2025 14:05 - 14:35 CEST

ABC Ballroom

Intrusion Detection and Prevention Systems (IDS/IPS) play a vital role in securing modern-day networks. However, as network speeds increase, software-based IDS/IPS like Suricata need to evolve to sustain their high performance in these new high-speed environments. Our work aims to accelerate open-source Suricata IDS by utilizing the rte_flow API in DPDK.

By taking advantage of rte_flow, we improve performance through various optimizations, such as encapsulation stripping or filtering user-predefined traffic.

To support Suricata's bypass of undesired flows, e.g., elephant or encrypted flows, we have also looked into the dynamic insertion of rte_flow rules. The new rte_flow support in Suricata enhances Suricata's already existing software filtering capabilities by adding a prefiltration step directly to the network card.

We evaluated Suricata's performance with our project Suricata-CI, an open-source toolset capable of testing Suricata with different traffic profiles.

This talk demonstrates how hardware acceleration can enhance network analysis efficiency in high-speed environments, showcases tools used to test these features, and presents the results we have achieved.

Speakers

Adam Kiripolský

Software engineer, Cesnet

Adam Kiripolský is a computer science student at the Faculty of Informatics, Masaryk University in Brno, Czech Republic. He is part of a research group at CESNET, where he focuses on accelerating Suricata using DPDK’s rte_flow API. Outside of research, he enjoys traveling, exploring... Read More →

Eliška Červinková

software engineer, Cesnet

Eliška is in her second year at the Faculty of Information Technology at BUT. She now manages Suricata-CI, the open-source testing framework, for their research group. One of her hobbies is coffee.

Thursday May 8, 2025 14:05 - 14:35 CEST
ABC Ballroom

Session Presentations

14:40 CEST

Service Chaining With HW Acceleration in Virtualized Environments - Roni Bar Yanai, NVIDIA

Thursday May 8, 2025 14:40 - 15:10 CEST

ABC Ballroom

In virtualized environments, a hypervisor-based switch provides the network fabric, often fully accelerated by NIC hardware. A common approach to extending its functionality is service chaining, where packets traveling to or from a VM/container pass through additional processing stages such as firewalling, encryption, routing, and more.

However, even with hardware acceleration, multiple packet transitions (e.g., Wire-to-FW, FW-to-Switch, Switch-to-VM) introduce processing overhead and limit performance, making it difficult to fully leverage hardware offload. An alternative—embedding all functionality within the switch—reduces modularity and compartmentalization, forces a single implementation, prevents the use of off-the-shelf products, and complicates architecture and maintenance.

In this talk, we introduce a novel approach using the DPDK Flow API to create a single hardware-accelerated pipeline while maintaining full modularity and separation between security functions and other services. This solution optimizes service chaining for firewalls, encryption and additional network services, maximizing acceleration without sacrificing flexibility or architectural simplicity.

Speakers

Roni Bar Yanai

SW NIC Acceleration Architect, NVIDIA

I have over 20 years of experience in networking, virtualization, and hardware acceleration, specializing in high-performance packet processing and NIC offloading. I currently lead the software architecture for NIC acceleration, focusing on DPDK, flow management, and service chaining... Read More →

Thursday May 8, 2025 14:40 - 15:10 CEST
ABC Ballroom

Session Presentations

15:10 CEST

Break + Networking

Thursday May 8, 2025 15:10 - 15:40 CEST

ABC Ballroom Foyer

Thursday May 8, 2025 15:10 - 15:40 CEST
ABC Ballroom Foyer

Registration/Breaks/Special Events

15:40 CEST

Benefits of Rte_flow Groups Specialization for FPGA SmartNICs - Lukáš Kekely, DynaNIC

Thursday May 8, 2025 15:40 - 16:10 CEST

ABC Ballroom

RTE Flow is a software API that allows to offload packet processing into a SmartNIC. As more advanced SmartNICs are coming to the market, the significance of RTE Flow grows. Developers would like to use the RTE Flow in a generic way which pushes SmartNICs design to offer as universal support as possible. However, there is always a trade-off between universality and performance. DPU-based SmartNICS provide generic support of RTE Flow while sacrificing performance which might be a serious issue when it comes to wirespeed processing of short packets on 400G links.

FPGA SmartNICs are another platform to achieve this goal. FPGAs can provide wirespeed performance, however, they are limited by available resources. It is impractical to implement a fully general RTE Flow support in an FPGA. Instead, it is more beneficial to design an application-specific processing pipeline made of match-action tables optimized for a target use case. The tables can be represented by RTE Flow groups which allows developers to easily control the processing from the software point of view.

The idea will be presented in more detail covering the most important aspects of this approach.

Speakers

Lukáš Kekely

CTO, DynaNIC

Lukas is leading a team of engineers focused on FPGA SmartNIC acceleration. Goal is to bring FPGA closer to software developers working on high-speed network applications. Lukas has over a decade of experience managing research and application projects related to the FPGA technology... Read More →

Thursday May 8, 2025 15:40 - 16:10 CEST
ABC Ballroom

Session Presentations

16:15 CEST

Deep Dive Into Protocol Agnostic Filter Technologies on Ethernet Adapters With DPDK - Shobhi Jain, Intel Corporation & Timothy Miskell, Intel

Thursday May 8, 2025 16:15 - 16:45 CEST

ABC Ballroom

This presentation explains in-depth method/tools for calculating spec, mask and enabling the RSS feature and FDIR steering on any customized imbedded L2 headers scenario. As an example, presentation will walkthrough a real-world use case of an Arista’s deployment i.e. Arista’s customized precision time protocol (PTP ) timestamps packet headers. It will describe the method to calculate spec, mask, create Generic Flow commands and use them to add or delete flow rules to the network adapter hardware for Arista’s customized imbedded L2 headers scenario. And the same method can be used to configure any other similar/customized scenario. Currently, there are few documents available describing about generic flow but there isn’t much information available about how the mask and spec used in configuring these generic flows can be calculated and maps to each other. This results in limiting the use of protocol agnostic filters capability of an ethernet adapter. This presentation will help to understand the method of enabling the RSS feature and FDIR steering on any customized packet headers through protocol agnostic flow offloading method.

Speakers

Shobhi Jain

Software Engineer, Intel Corporation

Shobhi Jain is a Software Engineer in Networking group, and she has been with Intel from past 11 years. She has been working on DPDK related product development and has Master’s in VLSI Design.

Timothy Miskell

Cloud Software Architect, Intel

Tim Miskell is a Cloud Software Architect part of the NEX Networking Group and has been with Intel since 2018. Along with numerous IEEE papers on the topics of networking, security, and AI he is part of the Open Source Technology Lab that includes Intel, Red Hat, and his alma mater... Read More →

Thursday May 8, 2025 16:15 - 16:45 CEST
ABC Ballroom

Session Presentations

16:50 CEST

Flexible Parsing in Flow API - Dariusz Sosnowski, NVIDIA Corporation

Thursday May 8, 2025 16:50 - 17:20 CEST

ABC Ballroom

One of P4 strengths is in providing extensive protocol parsing flexibility. With its programming language specifically designed for parsing, P4 enables the creation of custom protocols and headers.

Relaxed Matching Mode and Flex Parser DPDK flow APIs with capabilities such as TLV (Type-Length-Value) support and modify flex field, allow for taking a substantial stride towards narrowing the gap with P4 in terms of protocol parsing flexibility. By relaxing constraints and introducing custom protocol parsing capabilities, DPDK flow API can offer an alternative approach that matches P4's advantages in this area. As a result, the DPDK flow API offers a viable alternative approach that effectively addresses advanced protocol parsing and customization requirements, aligning with industry requirements in this area.

Speakers

Dariusz Sosnowski

Software Engineer, NVIDIA Corporation

I work as a Software Engineer at NVIDIA, where my main focus is contributing to DPDK, mostly as mlx5 PMD developer and maintainer. My area of expertise is HW flow rule offloading.

Thursday May 8, 2025 16:50 - 17:20 CEST
ABC Ballroom

Session Presentations

17:25 CEST

Closing Remarks

Thursday May 8, 2025 17:25 - 17:30 CEST

ABC Ballroom

Thursday May 8, 2025 17:25 - 17:30 CEST
ABC Ballroom

Opening/Closing Remarks

18:00 CEST

Attendee Reception

Thursday May 8, 2025 18:00 - 21:00 CEST

TBD

Thursday May 8, 2025 18:00 - 21:00 CEST
TBD

Registration/Breaks/Special Events