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DPDK Summit 2025
8-9 May 2025 | Prague, Czech Republic
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Please note: This schedule is automatically displayed in Central European Time. To see the schedule in your preferred timezone, please select from the drop-down at the bottom of the menu to the right.

The schedule is subject to change.
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Friday, May 9
 

09:15 CEST

QoS for DPDK Based Cloud Native Router - Kiran KN & Shailender Sharma, Juniper Networks
Friday May 9, 2025 09:15 - 09:45 CEST
Containerized router is a software router accelerated for giving high performance using the DPDK library. A fundamental requirement for any router (software or hardware) is Quality of Service. In the case of hardware routers, the QOS is implemented in hardware ASICs. Many off-the-self NICs also support it, but it is highly dependent on the capability of the NICs. Moreover, in cloud environments, software NICs won’t have any such capability. So, for cloud native routers, it is best to implement it in software using software queues.

In this talk, we will describe how we are leveraging the DPDK APIs to provide end-to-end quality of service including classification, policing, rewrite, scheduling and shaping for providing QOS in a cloud native software router environment. We will also describe a new and scalable packet processing model for QOS packet scheduling. The end result is a highly scalable, optimal and flexible model to achieve software QOS for use-cases like 5G front haul and mid haul.
Speakers
avatar for Shailender Sharma

Shailender Sharma

Sr. Staff Software Engineer, Juniper Networks
https://www.linkedin.com/in/shailendersharma/
avatar for Kiran KN

Kiran KN

Principal Engineer, Juniper Networks
Kiran is a Principal engineer in Juniper networks with over 18 years of experience in the SDN/cloud/datapath domain. He is the datapath architect and is working on Juniper Cloud native router (datapath) from last 2 years. He is currently focusing of software routing in the 5G space... Read More →
Friday May 9, 2025 09:15 - 09:45 CEST
ABC Ballroom

09:50 CEST

How To Make a Data Center Switch Smarter With DPDK - Cristian Dumitrescu, Intel
Friday May 9, 2025 09:50 - 10:20 CEST
This session presents the Data Center Smart Switch use-case and looks at how the SONiC DASH pipeline can be implemented with a combination of flexible HW pipeline and programmable CPU cores on a smart NIC device, with the Intel IPU E2100 adapter provided as example.

Here DPDK can play a leading role in efficiently implementing some of the special stages of the SONiC DASH logical pipeline such as the connection tracking block that have critical performance requirements (as measured in millions of TCP/UDP connections per second) and this session summarizes the key learnings for a performant DPDK-based connection tracking implementation.
Speakers
avatar for Cristian Dumitrescu

Cristian Dumitrescu

SW Architect, Intel
Cristian Dumitrescu is a SW architect at Intel. His focus is data plane packet processing on CPUs and IPUs, with many contributions to the Data Plane Development Kit (DPDK) project around table lookup algorithms, traffic schedulers, P4-based flexible data plane frameworks and most... Read More →
Friday May 9, 2025 09:50 - 10:20 CEST
ABC Ballroom

10:50 CEST

Enhancing DPDK Performance and Efficiency With RISC-V Extensions - Liang Ma, ByteDance & Yuwei Zhang, Tiktok
Friday May 9, 2025 10:50 - 11:20 CEST
In this presentation, we explore the integration of advanced RISC-V extensions to enhance the performance and efficiency of DPDK.

1. CRC Implementation with Zbc Extension:
The RISC-V Zbc extension introduces instructions for carry-less multiplication, which can be leveraged to implement Cyclic Redundancy Check (CRC) in hardware.

2. Efficient Waiting with Zawrs Extension:
We demonstrate how to use Zawrs instructions to implement RISC-V-specific versions of the rte_wait_until_equal_* functions, including handling 16-bit values through pointer rounding and bit shifting. The Zawrs extension is also applicable to the DPDK power management library.

3. Prefetching with Zicbop Extension:
The RISC-V Zicbop extension introduces instructions for cache block operations, which can be utilized to implement the rte_prefetch* family of functions.

Through detailed examples and performance benchmarks, we illustrate the benefits of these RISC-V extensions in optimising DPDK operations. Attendees will gain insights into the practical implementation of these techniques and their impact on performance and energy efficiency in data plane applications.
Speakers
avatar for Yuwei Zhang

Yuwei Zhang

senior software engineer, Tiktok
mainly focus on network, kernel, kernel bypass area.
avatar for Liang Ma

Liang Ma

System software architect,, ByteDance
System software architect, experienced DPDK developer/ researcher
Friday May 9, 2025 10:50 - 11:20 CEST
ABC Ballroom

11:40 CEST

Rte_graph: Introduction To Feature Arc Abstraction - Nitin Saxena, Marvell Technology
Friday May 9, 2025 11:40 - 12:10 CEST
Feature arc abstraction[1] primarily aims to solve two use cases for rte_graph based applications: (a) It provides mechanism to add new protocols, as DPDK in-built nodes, which required to be enabled on a per interface basis (Example: IPsec etc.). Here interface refers to both physical port and virtual interface like VLAN/VXLAN etc. (b) It provides mechanism to facilitate application reusing DPDK in-built nodes without any code duplication. It proposes to add hook points in certain in-built nodes where application can eject packets (at a given networking layer) and may again inject same packet to different networking layer, after processing it.

This session will introduce usability and applicability of feature arc in rte_graph nodes and will try to discuss design decisions taken to achieve the same.

[1]: https://mails.dpdk.org/archives/dev/2025-January/311166.html
Speakers
avatar for Nitin Saxena

Nitin Saxena

Senior Principal Engineer, Marvell Technology
Nitin Saxena is working as a senior principal engineer at Marvell Technology, where he contributes to offload networking solutions to hardware. He has 18+ years of experience in LINUX, FD.io VPP, OVS and DPDK networking. He is passionate about software/hardware technologies that minimise... Read More →
Friday May 9, 2025 11:40 - 12:10 CEST
ABC Ballroom

15:30 CEST

The DPDK Test Suite (DTS): Our Experience Running It at the DPDK Community Lab - Patrick Robb, The UNH InterOperability Lab
Friday May 9, 2025 15:30 - 16:00 CEST
The DPDK test suite (DTS) is a testing framework and set of end to end tests for DPDK which can be employed by DPDK developers and by labs performing CI testing. Given a minimal user configuration of the DPDK options and nodes to test, DTS will control the nodes, and test different DPDK workloads according to the test definitions. The framework will run a subset of the tests based on NIC capability checks completed at runtime, and provide a standard set of testrun logs and testrun result summaries.
In this talk, I will share how we have been leveraging DTS in the Community Lab. It is intended both to demonstrate a practical example of how the testing framework can and should be used, as well as provide an opportunity to discuss lessons learned over the past year and the development targets going forward for the DTS group. At DPDK summit 2024 there was a DTS presentation given which explained some of the DTS APIs exposed to testsuite writers, and explained how writing test suites worked. Ideally this talk will follow up on and compliment that talk by providing a real world example of DTS usage.

Requested time: 25 minutes (20 minute talk, 5 minutes for questions)
Speakers
avatar for Patrick Robb

Patrick Robb

Technical Manager, The UNH InterOperability Lab
Patrick Robb is a technical service manager at the UNH InterOperability lab, and has been working as the DPDK Community Lab manager since 2022. Patrick is interested in continuing to grow the relevance and utility of the DPDK Community Lab, and also build engagement across the publicly... Read More →
Friday May 9, 2025 15:30 - 16:00 CEST
ABC Ballroom

16:20 CEST

Leveraging AI and RAG To Enhance DPDK Application Development - Ori Kam, Nvidia
Friday May 9, 2025 16:20 - 16:50 CEST
As AI reshapes software development, DPDK can harness Retrieval-Augmented Generation (RAG) to provide developers with real-time access to best practices, optimization techniques, and expert knowledge. This session explores how AI-powered tools can help DPDK users improve performance tuning, troubleshoot issues, and generate optimized code by leveraging vast repositories of DPDK know-how. Additionally, we will demonstrate how AI can accelerate development by generating fast, tailored sample applications and test cases, enabling developers to prototype, validate, and optimize DPDK-based solutions more efficiently.
Speakers
avatar for Ori Kam

Ori Kam

senior staff engineer, Nvidia
I have over 15 years of software development experience and for the last few years, my focus has been contributing to DPDK, where I’m the rte_flow maintainer, and developing DPDK applications. My area of expertise is offloading traffic to the HW.
Friday May 9, 2025 16:20 - 16:50 CEST
ABC Ballroom
 
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