Name: Benefits of Rte_flow Groups Specialization for FPGA SmartNICs - Lukáš Kekely, DynaNIC
Start: 2025-05-08T15:40:00+0200
End: 2025-05-08T16:10:00+0200

8-9 May 2025 | Prague, Czech Republic
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Thursday May 8, 2025 15:40 - 16:10 CEST

ABC Ballroom

RTE Flow is a software API that allows to offload packet processing into a SmartNIC. As more advanced SmartNICs are coming to the market, the significance of RTE Flow grows. Developers would like to use the RTE Flow in a generic way which pushes SmartNICs design to offer as universal support as possible. However, there is always a trade-off between universality and performance. DPU-based SmartNICS provide generic support of RTE Flow while sacrificing performance which might be a serious issue when it comes to wirespeed processing of short packets on 400G links.

FPGA SmartNICs are another platform to achieve this goal. FPGAs can provide wirespeed performance, however, they are limited by available resources. It is impractical to implement a fully general RTE Flow support in an FPGA. Instead, it is more beneficial to design an application-specific processing pipeline made of match-action tables optimized for a target use case. The tables can be represented by RTE Flow groups which allows developers to easily control the processing from the software point of view.

The idea will be presented in more detail covering the most important aspects of this approach.

Speakers

Lukáš Kekely

CTO, DynaNIC

Lukas is leading a team of engineers focused on FPGA SmartNIC acceleration. Goal is to bring FPGA closer to software developers working on high-speed network applications. Lukas has over a decade of experience managing research and application projects related to the FPGA technology... Read More →

Thursday May 8, 2025 15:40 - 16:10 CEST
ABC Ballroom

Session Presentations

DPDK Summit 2025

Lukáš Kekely

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