Name: Rte_graph: Introduction To Feature Arc Abstraction - Nitin Saxena, Marvell Technology
Start: 2025-05-09T11:40:00+0200
End: 2025-05-09T12:10:00+0200

8-9 May 2025 | Prague, Czech Republic
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Friday May 9, 2025 11:40 - 12:10 CEST

ABC Ballroom

Feature arc abstraction[1] primarily aims to solve two use cases for rte_graph based applications: (a) It provides mechanism to add new protocols, as DPDK in-built nodes, which required to be enabled on a per interface basis (Example: IPsec etc.). Here interface refers to both physical port and virtual interface like VLAN/VXLAN etc. (b) It provides mechanism to facilitate application reusing DPDK in-built nodes without any code duplication. It proposes to add hook points in certain in-built nodes where application can eject packets (at a given networking layer) and may again inject same packet to different networking layer, after processing it.

This session will introduce usability and applicability of feature arc in rte_graph nodes and will try to discuss design decisions taken to achieve the same.

[1]: https://mails.dpdk.org/archives/dev/2025-January/311166.html

Speakers

Nitin Saxena

Senior Principal Engineer, Marvell Technology

Nitin Saxena is working as a senior principal engineer at Marvell Technology, where he contributes to offload networking solutions to hardware. He has 18+ years of experience in LINUX, FD.io VPP, OVS and DPDK networking. He is passionate about software/hardware technologies that minimise... Read More →

Friday May 9, 2025 11:40 - 12:10 CEST
ABC Ballroom

Session Presentations

DPDK Summit 2025

Nitin Saxena

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