DPDK Summit 2025

Niagara Networks provides high-performance, high-reliability network visibility and traffic delivery solutions for the world's most demanding service provider and enterprise environments.

Vitaliy will share Niagara Networks' experience in extending standard ASIC processing capabilities by integrating specialized hardware modules with DPDK applications into a single unit to support advanced functionalities such as:

- Packet and flow slicing
- Traffic deduplication
- NetFlow and IPFIX
- Packet data masking
- Packet RegEx search
- L7 application filtering
- TLS decryption
- GTP 3G/4G traffic correlation

To achieve this, Vitaliy will cover:

- Custom hardware utilizing Ethernet controllers from Intel
- ASIC-to-Ethernet controller backplane connectivity
- OS integration and provisioning for DPDK applications
- Performance and optimization strategies, including:
a. OS tweaks
b. BIOS optimizations
c. DPDK application architecture optimizations
- Testing and CI:
a. Custom framework development
b. CI implementation on test servers instead of final hardware

In this tech talk, we benchmark connection tracking implementations by extending rte_hash based tables with advanced flow aging mechanisms. We compare aging algorithms like timer wheels, smart periodic scanning vs. LRU tables.
We define test cases based on telco traffic profiles using T-Rex traffic-gen and interpret the benchmark results.
Join us to gain insights into enhancing DPDK rte_hash with flow aging features.

In this presentation, we explore the integration of advanced RISC-V extensions to enhance the performance and efficiency of DPDK.

1. CRC Implementation with Zbc Extension:
The RISC-V Zbc extension introduces instructions for carry-less multiplication, which can be leveraged to implement Cyclic Redundancy Check (CRC) in hardware.

2. Efficient Waiting with Zawrs Extension:
We demonstrate how to use Zawrs instructions to implement RISC-V-specific versions of the rte_wait_until_equal_* functions, including handling 16-bit values through pointer rounding and bit shifting. The Zawrs extension is also applicable to the DPDK power management library.

3. Prefetching with Zicbop Extension:
The RISC-V Zicbop extension introduces instructions for cache block operations, which can be utilized to implement the rte_prefetch* family of functions.

Through detailed examples and performance benchmarks, we illustrate the benefits of these RISC-V extensions in optimising DPDK operations. Attendees will gain insights into the practical implementation of these techniques and their impact on performance and energy efficiency in data plane applications.

Feature arc abstraction[1] primarily aims to solve two use cases for rte_graph based applications: (a) It provides mechanism to add new protocols, as DPDK in-built nodes, which required to be enabled on a per interface basis (Example: IPsec etc.). Here interface refers to both physical port and virtual interface like VLAN/IPIP etc. (b) It also provides mechanism to facilitate application reusing DPDK in-built nodes without any code duplication. It proposes to add hook points in certain in-built nodes where application can eject packets (at a given networking layer) and may again inject same packet to different networking layer, after processing it.

This session will introduce usability and applicability of feature arc in rte_graph nodes and will try to discuss design decisions taken to achieve the same.

[1]: https://mails.dpdk.org/archives/dev/2025-January/311166.html